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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>E:\FPGA\Tang20K\ethernet\ethernet\impl\gwsynthesis\ethernet.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>E:\FPGA\Tang20K\ethernet\ethernet\src\ethernet.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>E:\FPGA\Tang20K\ethernet\ethernet\src\timing.sdc</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-4 Education</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Dec 11 23:41:53 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>1832</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>1567</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>23</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>sys_clk</td>
<td>Base</td>
<td>37.037</td>
<td>27.000
<td>0.000</td>
<td>18.518</td>
<td></td>
<td></td>
<td>sys_clk </td>
</tr>
<tr>
<td>clk1m</td>
<td>Base</td>
<td>1000.000</td>
<td>1.000
<td>0.000</td>
<td>500.000</td>
<td></td>
<td></td>
<td>mdc_d </td>
</tr>
<tr>
<td>clk25m</td>
<td>Base</td>
<td>40.000</td>
<td>25.000
<td>0.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td>clk_25m </td>
</tr>
<tr>
<td>eth_clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>eth_clk </td>
</tr>
<tr>
<td>n4_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F </td>
</tr>
<tr>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk1m</td>
<td>1.000(MHz)</td>
<td>284.232(MHz)</td>
<td>3</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>clk25m</td>
<td>25.000(MHz)</td>
<td>123.682(MHz)</td>
<td>8</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>eth_clk</td>
<td>50.000(MHz)</td>
<td>145.247(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>4</td>
<td>n4_6</td>
<td>100.000(MHz)</td>
<td>357.857(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
</table>
<h4>No timing paths to get frequency of sys_clk!</h4>
<h4>No timing paths to get frequency of fifo_2048x32_inst/fifo_inst/wfull_val!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>sys_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>sys_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk1m</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk1m</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk25m</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk25m</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>eth_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>eth_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>n4_6</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>n4_6</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>1.048</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_8_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>3.097</td>
</tr>
<tr>
<td>2</td>
<td>1.048</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_9_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>3.097</td>
</tr>
<tr>
<td>3</td>
<td>1.048</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_8_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>3.097</td>
</tr>
<tr>
<td>4</td>
<td>1.048</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_9_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>3.097</td>
</tr>
<tr>
<td>5</td>
<td>1.048</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_11_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>3.097</td>
</tr>
<tr>
<td>6</td>
<td>1.050</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_10_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>3.095</td>
</tr>
<tr>
<td>7</td>
<td>1.217</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_2_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>2.929</td>
</tr>
<tr>
<td>8</td>
<td>1.276</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_1_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>2.870</td>
</tr>
<tr>
<td>9</td>
<td>1.304</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_7_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>2.841</td>
</tr>
<tr>
<td>10</td>
<td>1.453</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_10_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>2.692</td>
</tr>
<tr>
<td>11</td>
<td>1.509</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_2_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>2.636</td>
</tr>
<tr>
<td>12</td>
<td>1.584</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_7_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>2.562</td>
</tr>
<tr>
<td>13</td>
<td>1.686</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_0_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>2.459</td>
</tr>
<tr>
<td>14</td>
<td>1.740</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_1_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>2.405</td>
</tr>
<tr>
<td>15</td>
<td>1.850</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/D</td>
<td>clk25m:[R]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>5.000</td>
<td>-0.784</td>
<td>3.864</td>
</tr>
<tr>
<td>16</td>
<td>2.003</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_6_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>2.143</td>
</tr>
<tr>
<td>17</td>
<td>2.473</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_0_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>1.673</td>
</tr>
<tr>
<td>18</td>
<td>2.571</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/CEA</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>1.523</td>
</tr>
<tr>
<td>19</td>
<td>2.574</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CEA</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>1.520</td>
</tr>
<tr>
<td>20</td>
<td>2.616</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_6_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>1.529</td>
</tr>
<tr>
<td>21</td>
<td>2.630</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_3_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>1.516</td>
</tr>
<tr>
<td>22</td>
<td>2.630</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_4_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>1.516</td>
</tr>
<tr>
<td>23</td>
<td>2.630</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_5_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>1.516</td>
</tr>
<tr>
<td>24</td>
<td>2.741</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Full_s0/D</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>1.405</td>
</tr>
<tr>
<td>25</td>
<td>2.745</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s/CEA</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>clk25m:[R]</td>
<td>5.000</td>
<td>0.784</td>
<td>1.349</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.199</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_18_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[2]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.448</td>
</tr>
<tr>
<td>2</td>
<td>0.215</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_23_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[7]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>3</td>
<td>0.215</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_22_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[6]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>4</td>
<td>0.218</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_7_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/ADB[10]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.336</td>
</tr>
<tr>
<td>5</td>
<td>0.224</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_5_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/ADB[8]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.342</td>
</tr>
<tr>
<td>6</td>
<td>0.225</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_4_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADB[7]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.343</td>
</tr>
<tr>
<td>7</td>
<td>0.238</td>
<td>rmii_to_mii_inst/rx_dv_ture_reg_s0/Q</td>
<td>rmii_to_mii_inst/eth_rx_dv_s0/D</td>
<td>eth_clk:[R]</td>
<td>n4_6:[R]</td>
<td>0.000</td>
<td>-0.271</td>
<td>0.555</td>
</tr>
<tr>
<td>8</td>
<td>0.324</td>
<td>rtl8201_initialize_inst0/phy_rdy_s0/Q</td>
<td>rtl8201_initialize_inst0/SMI_trg_s0/CE</td>
<td>clk1m:[R]</td>
<td>clk1m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.335</td>
</tr>
<tr>
<td>9</td>
<td>0.325</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_16_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[0]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.574</td>
</tr>
<tr>
<td>10</td>
<td>0.337</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_21_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[5]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.586</td>
</tr>
<tr>
<td>11</td>
<td>0.337</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_19_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[3]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.586</td>
</tr>
<tr>
<td>12</td>
<td>0.340</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_20_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[4]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.589</td>
</tr>
<tr>
<td>13</td>
<td>0.340</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_17_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[1]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.589</td>
</tr>
<tr>
<td>14</td>
<td>0.349</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_30_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s/DI[6]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.598</td>
</tr>
<tr>
<td>15</td>
<td>0.350</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_2_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADA[5]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.468</td>
</tr>
<tr>
<td>16</td>
<td>0.351</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_8_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADB[11]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.469</td>
</tr>
<tr>
<td>17</td>
<td>0.351</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_5_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADA[8]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.469</td>
</tr>
<tr>
<td>18</td>
<td>0.351</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_8_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/ADB[11]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.469</td>
</tr>
<tr>
<td>19</td>
<td>0.352</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_3_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADA[6]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.470</td>
</tr>
<tr>
<td>20</td>
<td>0.352</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_10_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADA[13]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.470</td>
</tr>
<tr>
<td>21</td>
<td>0.352</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_10_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/ADB[13]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.470</td>
</tr>
<tr>
<td>22</td>
<td>0.352</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_9_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/ADB[12]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.470</td>
</tr>
<tr>
<td>23</td>
<td>0.352</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_0_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADB[3]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.470</td>
</tr>
<tr>
<td>24</td>
<td>0.352</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_0_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADA[3]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.470</td>
</tr>
<tr>
<td>25</td>
<td>0.352</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_0_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/ADB[3]</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.470</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>4.691</td>
<td>fifo_2048x32_inst/fifo_inst/reset_w_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/CLEAR</td>
<td>clk25m:[F]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
<td>5.000</td>
<td>-0.656</td>
<td>0.895</td>
</tr>
<tr>
<td>2</td>
<td>6.678</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Empty_s0/PRESET</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>2.511</td>
</tr>
<tr>
<td>3</td>
<td>6.678</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rempty_val1_s0/PRESET</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>2.511</td>
</tr>
<tr>
<td>4</td>
<td>7.227</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s/RESETB</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>5</td>
<td>7.227</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/RESETB</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>6</td>
<td>7.227</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/RESETB</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>7</td>
<td>7.227</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/RESETB</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>8</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_0_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>9</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_1_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>10</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_2_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>11</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>12</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_4_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>13</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_5_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>14</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_6_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>15</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_7_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>16</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_8_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>17</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_9_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>18</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_10_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>19</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_0_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>20</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_1_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>21</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_2_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>22</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_3_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>23</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_4_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>24</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_5_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
<tr>
<td>25</td>
<td>7.630</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_6_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>10.000</td>
<td>0.741</td>
<td>1.559</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.450</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/Q</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_4_s0/CLEAR</td>
<td>clk1m:[R]</td>
<td>clk1m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.461</td>
</tr>
<tr>
<td>2</td>
<td>0.450</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/Q</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_6_s0/CLEAR</td>
<td>clk1m:[R]</td>
<td>clk1m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.461</td>
</tr>
<tr>
<td>3</td>
<td>0.467</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/Q</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_7_s0/CLEAR</td>
<td>clk1m:[R]</td>
<td>clk1m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.478</td>
</tr>
<tr>
<td>4</td>
<td>0.467</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/Q</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_0_s0/CLEAR</td>
<td>clk1m:[R]</td>
<td>clk1m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.478</td>
</tr>
<tr>
<td>5</td>
<td>0.467</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/Q</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_3_s0/CLEAR</td>
<td>clk1m:[R]</td>
<td>clk1m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.478</td>
</tr>
<tr>
<td>6</td>
<td>0.467</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/Q</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_5_s0/CLEAR</td>
<td>clk1m:[R]</td>
<td>clk1m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.478</td>
</tr>
<tr>
<td>7</td>
<td>0.587</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/Q</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ready_s5/CLEAR</td>
<td>clk1m:[R]</td>
<td>clk1m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.598</td>
</tr>
<tr>
<td>8</td>
<td>0.587</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/Q</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_1_s0/CLEAR</td>
<td>clk1m:[R]</td>
<td>clk1m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.598</td>
</tr>
<tr>
<td>9</td>
<td>0.587</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/Q</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_2_s0/CLEAR</td>
<td>clk1m:[R]</td>
<td>clk1m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.598</td>
</tr>
<tr>
<td>10</td>
<td>0.705</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/Q</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ack_s1/CLEAR</td>
<td>clk1m:[R]</td>
<td>clk1m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.716</td>
</tr>
<tr>
<td>11</td>
<td>1.047</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/Q</td>
<td>rtl8201_initialize_inst0/mdio_inst0/rmdio_s0/PRESET</td>
<td>clk1m:[R]</td>
<td>clk1m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>12</td>
<td>1.440</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Full_s1/PRESET</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.451</td>
</tr>
<tr>
<td>13</td>
<td>1.440</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s1/PRESET</td>
<td>clk25m:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.451</td>
</tr>
<tr>
<td>14</td>
<td>1.548</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s/RESETB</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.537</td>
<td>1.058</td>
</tr>
<tr>
<td>15</td>
<td>1.548</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/RESETB</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.537</td>
<td>1.058</td>
</tr>
<tr>
<td>16</td>
<td>1.548</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/RESETB</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.537</td>
<td>1.058</td>
</tr>
<tr>
<td>17</td>
<td>1.548</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/RESETB</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.537</td>
<td>1.058</td>
</tr>
<tr>
<td>18</td>
<td>1.549</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_0_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.537</td>
<td>1.058</td>
</tr>
<tr>
<td>19</td>
<td>1.549</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_1_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.537</td>
<td>1.058</td>
</tr>
<tr>
<td>20</td>
<td>1.549</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_2_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.537</td>
<td>1.058</td>
</tr>
<tr>
<td>21</td>
<td>1.549</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.537</td>
<td>1.058</td>
</tr>
<tr>
<td>22</td>
<td>1.549</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_4_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.537</td>
<td>1.058</td>
</tr>
<tr>
<td>23</td>
<td>1.549</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_5_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.537</td>
<td>1.058</td>
</tr>
<tr>
<td>24</td>
<td>1.549</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_6_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.537</td>
<td>1.058</td>
</tr>
<tr>
<td>25</td>
<td>1.549</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_7_s0/CLEAR</td>
<td>n4_6:[R]</td>
<td>clk25m:[R]</td>
<td>0.000</td>
<td>0.537</td>
<td>1.058</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>3.379</td>
<td>4.379</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>n4_6</td>
<td>rmii_to_mii_inst/eth_rx_data_3_s0</td>
</tr>
<tr>
<td>2</td>
<td>3.379</td>
<td>4.379</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>n4_6</td>
<td>rmii_to_mii_inst/eth_rx_data_2_s0</td>
</tr>
<tr>
<td>3</td>
<td>3.379</td>
<td>4.379</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>n4_6</td>
<td>rmii_to_mii_inst/eth_rx_data_0_s0</td>
</tr>
<tr>
<td>4</td>
<td>3.382</td>
<td>4.382</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>n4_6</td>
<td>rmii_to_mii_inst/eth_rx_dv_s0</td>
</tr>
<tr>
<td>5</td>
<td>3.382</td>
<td>4.382</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>n4_6</td>
<td>rmii_to_mii_inst/eth_rx_data_1_s0</td>
</tr>
<tr>
<td>6</td>
<td>3.382</td>
<td>4.382</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>n4_6</td>
<td>eth_udp_mii_inst/ip_receive_inst/eth_rxdv_reg_s0</td>
</tr>
<tr>
<td>7</td>
<td>3.382</td>
<td>4.382</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>n4_6</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_0_s0</td>
</tr>
<tr>
<td>8</td>
<td>3.382</td>
<td>4.382</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>n4_6</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td>9</td>
<td>3.382</td>
<td>4.382</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>n4_6</td>
<td>eth_udp_mii_inst/ip_receive_inst/eth_rx_data_reg_3_s0</td>
</tr>
<tr>
<td>10</td>
<td>3.382</td>
<td>4.382</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>n4_6</td>
<td>eth_udp_mii_inst/ip_receive_inst/eth_rx_data_reg_1_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.048</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.697</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>37.566</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R27C25[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>38.148</td>
<td>0.582</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/I0</td>
</tr>
<tr>
<td>38.703</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>R29C26[1][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/F</td>
</tr>
<tr>
<td>39.148</td>
<td>0.445</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_8_s3/I0</td>
</tr>
<tr>
<td>39.697</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_8_s3/F</td>
</tr>
<tr>
<td>39.697</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_8_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_8_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C27[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.659, 53.565%; route: 1.206, 38.945%; tC2Q: 0.232, 7.491%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.048</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.697</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>37.566</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R27C25[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>38.148</td>
<td>0.582</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/I0</td>
</tr>
<tr>
<td>38.703</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>R29C26[1][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/F</td>
</tr>
<tr>
<td>39.148</td>
<td>0.445</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C27[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_9_s3/I0</td>
</tr>
<tr>
<td>39.697</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C27[2][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_9_s3/F</td>
</tr>
<tr>
<td>39.697</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[2][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_9_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_9_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C27[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.659, 53.565%; route: 1.206, 38.945%; tC2Q: 0.232, 7.491%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.048</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.697</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>37.566</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R27C25[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>38.148</td>
<td>0.582</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/I0</td>
</tr>
<tr>
<td>38.703</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>R29C26[1][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/F</td>
</tr>
<tr>
<td>39.148</td>
<td>0.445</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C27[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s0/I0</td>
</tr>
<tr>
<td>39.697</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C27[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s0/F</td>
</tr>
<tr>
<td>39.697</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wptr_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_8_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wptr_8_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C27[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.659, 53.565%; route: 1.206, 38.945%; tC2Q: 0.232, 7.491%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.048</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.697</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>37.566</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R27C25[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>38.148</td>
<td>0.582</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/I0</td>
</tr>
<tr>
<td>38.703</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>R29C26[1][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/F</td>
</tr>
<tr>
<td>39.148</td>
<td>0.445</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C27[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_9_s0/I0</td>
</tr>
<tr>
<td>39.697</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C27[2][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_9_s0/F</td>
</tr>
<tr>
<td>39.697</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wptr_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_9_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wptr_9_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C27[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.659, 53.565%; route: 1.206, 38.945%; tC2Q: 0.232, 7.491%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.048</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.697</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>37.566</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R27C25[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>38.148</td>
<td>0.582</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/I0</td>
</tr>
<tr>
<td>38.703</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>R29C26[1][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/F</td>
</tr>
<tr>
<td>39.148</td>
<td>0.445</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_11_s2/I0</td>
</tr>
<tr>
<td>39.697</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_11_s2/F</td>
</tr>
<tr>
<td>39.697</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wptr_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_11_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wptr_11_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C27[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.659, 53.565%; route: 1.206, 38.945%; tC2Q: 0.232, 7.491%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.050</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.695</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>37.566</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R27C25[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>38.148</td>
<td>0.582</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/I0</td>
</tr>
<tr>
<td>38.703</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>R29C26[1][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/F</td>
</tr>
<tr>
<td>39.125</td>
<td>0.422</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_10_s0/I0</td>
</tr>
<tr>
<td>39.695</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C25[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_10_s0/F</td>
</tr>
<tr>
<td>39.695</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wptr_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_10_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wptr_10_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.680, 54.276%; route: 1.183, 38.228%; tC2Q: 0.232, 7.495%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.217</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.528</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>36.994</td>
<td>0.163</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/n30_s1/I2</td>
</tr>
<tr>
<td>37.511</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R27C24[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n30_s1/F</td>
</tr>
<tr>
<td>38.201</td>
<td>0.690</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[3][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_2_s3/I0</td>
</tr>
<tr>
<td>38.756</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R29C26[3][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_2_s3/F</td>
</tr>
<tr>
<td>39.528</td>
<td>0.772</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C25[2][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_2_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_2_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C25[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.072, 36.601%; route: 1.625, 55.478%; tC2Q: 0.232, 7.921%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.276</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.469</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>36.994</td>
<td>0.163</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/n30_s1/I2</td>
</tr>
<tr>
<td>37.511</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R27C24[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n30_s1/F</td>
</tr>
<tr>
<td>38.201</td>
<td>0.690</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[3][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_2_s3/I0</td>
</tr>
<tr>
<td>38.756</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R29C26[3][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_2_s3/F</td>
</tr>
<tr>
<td>39.007</td>
<td>0.252</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C24[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_1_s1/I3</td>
</tr>
<tr>
<td>39.469</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C24[1][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_1_s1/F</td>
</tr>
<tr>
<td>39.469</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C24[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wptr_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C24[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_1_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wptr_1_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C24[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.534, 53.449%; route: 1.104, 38.467%; tC2Q: 0.232, 8.084%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.304</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.441</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>37.566</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R27C25[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>38.148</td>
<td>0.582</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_7_s1/I0</td>
</tr>
<tr>
<td>38.697</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R29C26[2][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_7_s1/F</td>
</tr>
<tr>
<td>38.871</td>
<td>0.174</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_7_s0/I0</td>
</tr>
<tr>
<td>39.441</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_7_s0/F</td>
</tr>
<tr>
<td>39.441</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wptr_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_7_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wptr_7_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C27[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.674, 58.919%; route: 0.935, 32.915%; tC2Q: 0.232, 8.166%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.453</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.292</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>37.566</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R27C25[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>38.148</td>
<td>0.582</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/I0</td>
</tr>
<tr>
<td>38.718</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>7</td>
<td>R29C26[1][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_8_s1/F</td>
</tr>
<tr>
<td>38.722</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_10_s4/I0</td>
</tr>
<tr>
<td>39.292</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C26[0][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_10_s4/F</td>
</tr>
<tr>
<td>39.292</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_10_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_10_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C26[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.695, 62.957%; route: 0.765, 28.426%; tC2Q: 0.232, 8.617%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.509</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.236</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>36.994</td>
<td>0.163</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/n30_s1/I2</td>
</tr>
<tr>
<td>37.511</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R27C24[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n30_s1/F</td>
</tr>
<tr>
<td>38.201</td>
<td>0.690</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[3][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_2_s3/I0</td>
</tr>
<tr>
<td>38.771</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R29C26[3][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_2_s3/F</td>
</tr>
<tr>
<td>38.774</td>
<td>0.003</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_2_s0/I1</td>
</tr>
<tr>
<td>39.236</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C26[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_2_s0/F</td>
</tr>
<tr>
<td>39.236</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wptr_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_2_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wptr_2_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C26[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.549, 58.759%; route: 0.855, 32.440%; tC2Q: 0.232, 8.801%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.584</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.161</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>37.566</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R27C25[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>38.148</td>
<td>0.582</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C26[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_7_s1/I0</td>
</tr>
<tr>
<td>38.697</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R29C26[2][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_7_s1/F</td>
</tr>
<tr>
<td>38.699</td>
<td>0.003</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_7_s3/I0</td>
</tr>
<tr>
<td>39.161</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C26[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_7_s3/F</td>
</tr>
<tr>
<td>39.161</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_7_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_7_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C26[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.566, 61.124%; route: 0.764, 29.820%; tC2Q: 0.232, 9.055%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.686</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.059</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>36.994</td>
<td>0.163</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/n30_s1/I2</td>
</tr>
<tr>
<td>37.511</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R27C24[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n30_s1/F</td>
</tr>
<tr>
<td>37.958</td>
<td>0.447</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C25[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_1_s3/I0</td>
</tr>
<tr>
<td>38.507</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R29C25[2][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_1_s3/F</td>
</tr>
<tr>
<td>38.510</td>
<td>0.003</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_0_s1/I2</td>
</tr>
<tr>
<td>39.059</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C25[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_0_s1/F</td>
</tr>
<tr>
<td>39.059</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wptr_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_0_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wptr_0_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C25[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.615, 65.665%; route: 0.612, 24.902%; tC2Q: 0.232, 9.433%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.740</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>39.005</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>36.994</td>
<td>0.163</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/n30_s1/I2</td>
</tr>
<tr>
<td>37.511</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R27C24[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n30_s1/F</td>
</tr>
<tr>
<td>37.958</td>
<td>0.447</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C25[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_1_s3/I0</td>
</tr>
<tr>
<td>38.475</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R29C25[2][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_1_s3/F</td>
</tr>
<tr>
<td>39.005</td>
<td>0.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C25[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_1_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_1_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C25[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.034, 42.986%; route: 1.139, 47.369%; tC2Q: 0.232, 9.645%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.850</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.679</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>6.529</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C24[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_1_s0/CLK</td>
</tr>
<tr>
<td>1.047</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R29C24[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wptr_1_s0/Q</td>
</tr>
<tr>
<td>1.948</td>
<td>0.901</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C20[3][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s6/I0</td>
</tr>
<tr>
<td>2.503</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R29C20[3][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/wfull_val_s6/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.413</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C22[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s1/I2</td>
</tr>
<tr>
<td>3.287</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R29C22[2][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/wfull_val_s1/F</td>
</tr>
<tr>
<td>3.540</td>
<td>0.253</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C22[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n678_s0/I3</td>
</tr>
<tr>
<td>4.057</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n678_s0/F</td>
</tr>
<tr>
<td>4.679</td>
<td>0.623</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>6.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>6.564</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td>6.529</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.443, 37.342%; route: 2.189, 56.655%; tC2Q: 0.232, 6.004%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.003</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>38.742</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>37.566</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R27C25[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>37.817</td>
<td>0.252</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C25[3][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_6_s1/I0</td>
</tr>
<tr>
<td>38.279</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C25[3][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_6_s1/F</td>
</tr>
<tr>
<td>38.280</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_6_s0/I0</td>
</tr>
<tr>
<td>38.742</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R29C25[1][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_6_s0/F</td>
</tr>
<tr>
<td>38.742</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wptr_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_6_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wptr_6_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C25[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wptr_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.479, 69.016%; route: 0.432, 20.158%; tC2Q: 0.232, 10.826%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.473</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>38.272</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>36.994</td>
<td>0.163</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/n30_s1/I2</td>
</tr>
<tr>
<td>37.543</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R27C24[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n30_s1/F</td>
</tr>
<tr>
<td>37.723</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C25[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_0_s3/I0</td>
</tr>
<tr>
<td>38.272</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R27C25[0][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_0_s3/F</td>
</tr>
<tr>
<td>38.272</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C25[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C25[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_0_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_0_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C25[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.098, 65.645%; route: 0.343, 20.484%; tC2Q: 0.232, 13.870%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.571</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>38.122</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.693</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>36.994</td>
<td>0.163</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/n30_s1/I2</td>
</tr>
<tr>
<td>37.543</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R27C24[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n30_s1/F</td>
</tr>
<tr>
<td>38.122</td>
<td>0.579</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/CEA</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKA</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
<tr>
<td>40.693</td>
<td>-0.087</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.549, 36.047%; route: 0.742, 48.720%; tC2Q: 0.232, 15.233%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.574</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>38.119</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.693</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>36.994</td>
<td>0.163</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/n30_s1/I2</td>
</tr>
<tr>
<td>37.543</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R27C24[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n30_s1/F</td>
</tr>
<tr>
<td>38.119</td>
<td>0.576</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CEA</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKA</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
<tr>
<td>40.693</td>
<td>-0.087</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.549, 36.122%; route: 0.739, 48.614%; tC2Q: 0.232, 15.265%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.616</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>38.129</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C25[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_d_s/I2</td>
</tr>
<tr>
<td>37.581</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>4</td>
<td>R27C25[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Full_d_s/F</td>
</tr>
<tr>
<td>37.758</td>
<td>0.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C26[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_6_s4/I0</td>
</tr>
<tr>
<td>38.129</td>
<td>0.371</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R27C26[2][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_6_s4/F</td>
</tr>
<tr>
<td>38.129</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C26[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C26[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_6_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_6_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C26[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.941, 61.537%; route: 0.356, 23.291%; tC2Q: 0.232, 15.172%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>38.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_2_s3/I2</td>
</tr>
<tr>
<td>37.382</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>R27C24[2][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_2_s3/F</td>
</tr>
<tr>
<td>37.653</td>
<td>0.272</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_3_s3/I0</td>
</tr>
<tr>
<td>38.115</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C24[0][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_3_s3/F</td>
</tr>
<tr>
<td>38.115</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_3_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_3_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.833, 54.951%; route: 0.451, 29.744%; tC2Q: 0.232, 15.304%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>38.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_2_s3/I2</td>
</tr>
<tr>
<td>37.382</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>R27C24[2][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_2_s3/F</td>
</tr>
<tr>
<td>37.653</td>
<td>0.272</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C24[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_4_s3/I0</td>
</tr>
<tr>
<td>38.115</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C24[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_4_s3/F</td>
</tr>
<tr>
<td>38.115</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_4_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_4_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C24[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.833, 54.951%; route: 0.451, 29.744%; tC2Q: 0.232, 15.304%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>38.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.011</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wgraynext_2_s3/I2</td>
</tr>
<tr>
<td>37.382</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>R27C24[2][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wgraynext_2_s3/F</td>
</tr>
<tr>
<td>37.653</td>
<td>0.272</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C24[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbinnext_5_s4/I0</td>
</tr>
<tr>
<td>38.115</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R29C24[1][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/Equal.wbinnext_5_s4/F</td>
</tr>
<tr>
<td>38.115</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C24[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C24[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_5_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_5_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C24[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.833, 54.951%; route: 0.451, 29.744%; tC2Q: 0.232, 15.304%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.741</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>38.004</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Full_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>37.087</td>
<td>0.256</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C26[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s6/I2</td>
</tr>
<tr>
<td>37.458</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R27C26[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/wfull_val1_s6/F</td>
</tr>
<tr>
<td>38.004</td>
<td>0.546</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C25[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Full_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C25[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Full_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C25[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.371, 26.412%; route: 0.802, 57.072%; tC2Q: 0.232, 16.516%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.745</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>37.948</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.693</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>35.000</td>
<td>35.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>35.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>36.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>36.831</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/Q</td>
</tr>
<tr>
<td>36.994</td>
<td>0.163</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/n30_s1/I2</td>
</tr>
<tr>
<td>37.543</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R27C24[0][B]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n30_s1/F</td>
</tr>
<tr>
<td>37.948</td>
<td>0.405</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[8]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s/CEA</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[8]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKA</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s</td>
</tr>
<tr>
<td>40.693</td>
<td>-0.087</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[8]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.784</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.549, 40.706%; route: 0.568, 42.092%; tC2Q: 0.232, 17.202%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.199</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.042</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_18_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C23[1][A]</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_18_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R24C23[1][A]</td>
<td style=" font-weight:bold;">eth_udp_mii_inst/ip_receive_inst/rec_data_18_s0/Q</td>
</tr>
<tr>
<td>1.042</td>
<td>0.246</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.843</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.246, 54.955%; tC2Q: 0.202, 45.045%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_23_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C23[0][B]</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_23_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R25C23[0][B]</td>
<td style=" font-weight:bold;">eth_udp_mii_inst/ip_receive_inst/rec_data_23_s0/Q</td>
</tr>
<tr>
<td>1.057</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[7]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.843</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.057</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_22_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C23[2][A]</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_22_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R25C23[2][A]</td>
<td style=" font-weight:bold;">eth_udp_mii_inst/ip_receive_inst/rec_data_22_s0/Q</td>
</tr>
<tr>
<td>1.057</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[6]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.843</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.218</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.930</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C17[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_7_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>11</td>
<td>R29C17[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_7_s0/Q</td>
</tr>
<tr>
<td>0.930</td>
<td>0.135</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/ADB[10]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.135, 40.180%; tC2Q: 0.201, 59.820%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.224</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.935</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C20[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_5_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>7</td>
<td>R27C20[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_5_s0/Q</td>
</tr>
<tr>
<td>0.935</td>
<td>0.141</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/ADB[8]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKB</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.141, 41.164%; tC2Q: 0.201, 58.836%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.225</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.936</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_4_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R29C23[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_4_s0/Q</td>
</tr>
<tr>
<td>0.936</td>
<td>0.142</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADB[7]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKB</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.142, 41.325%; tC2Q: 0.201, 58.675%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.238</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.415</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.177</td>
</tr>
<tr>
<td class="label">From</td>
<td>rmii_to_mii_inst/rx_dv_ture_reg_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rmii_to_mii_inst/eth_rx_dv_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>eth_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n4_6:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>eth_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL27[A]</td>
<td>eth_clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>28</td>
<td>IOL27[A]</td>
<td>eth_clk_ibuf/O</td>
</tr>
<tr>
<td>0.860</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C39[1][A]</td>
<td>rmii_to_mii_inst/rx_dv_ture_reg_s0/CLK</td>
</tr>
<tr>
<td>1.061</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R31C39[1][A]</td>
<td style=" font-weight:bold;">rmii_to_mii_inst/rx_dv_ture_reg_s0/Q</td>
</tr>
<tr>
<td>1.415</td>
<td>0.354</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C39[0][B]</td>
<td style=" font-weight:bold;">rmii_to_mii_inst/eth_rx_dv_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>1.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C39[0][B]</td>
<td>rmii_to_mii_inst/eth_rx_dv_s0/CLK</td>
</tr>
<tr>
<td>1.166</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rmii_to_mii_inst/eth_rx_dv_s0</td>
</tr>
<tr>
<td>1.177</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C39[0][B]</td>
<td>rmii_to_mii_inst/eth_rx_dv_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.271</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.354, 63.777%; tC2Q: 0.201, 36.223%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.324</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.520</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.195</td>
</tr>
<tr>
<td class="label">From</td>
<td>rtl8201_initialize_inst0/phy_rdy_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rtl8201_initialize_inst0/SMI_trg_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk1m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk1m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[1][A]</td>
<td>rtl8201_initialize_inst0/phy_rdy_s0/CLK</td>
</tr>
<tr>
<td>0.386</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C27[1][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/phy_rdy_s0/Q</td>
</tr>
<tr>
<td>0.520</td>
<td>0.133</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[0][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/SMI_trg_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C27[0][A]</td>
<td>rtl8201_initialize_inst0/SMI_trg_s0/CLK</td>
</tr>
<tr>
<td>0.195</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C27[0][A]</td>
<td>rtl8201_initialize_inst0/SMI_trg_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.325</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.168</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_16_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C23[1][B]</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_16_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R24C23[1][B]</td>
<td style=" font-weight:bold;">eth_udp_mii_inst/ip_receive_inst/rec_data_16_s0/Q</td>
</tr>
<tr>
<td>1.168</td>
<td>0.372</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.843</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.372, 64.834%; tC2Q: 0.202, 35.166%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.337</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.179</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C23[1][B]</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_21_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R25C23[1][B]</td>
<td style=" font-weight:bold;">eth_udp_mii_inst/ip_receive_inst/rec_data_21_s0/Q</td>
</tr>
<tr>
<td>1.179</td>
<td>0.384</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[5]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.843</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.384, 65.506%; tC2Q: 0.202, 34.494%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.337</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.179</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_19_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C23[0][A]</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_19_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R24C23[0][A]</td>
<td style=" font-weight:bold;">eth_udp_mii_inst/ip_receive_inst/rec_data_19_s0/Q</td>
</tr>
<tr>
<td>1.179</td>
<td>0.384</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.843</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.384, 65.506%; tC2Q: 0.202, 34.494%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.340</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.183</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_20_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C23[1][A]</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_20_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R25C23[1][A]</td>
<td style=" font-weight:bold;">eth_udp_mii_inst/ip_receive_inst/rec_data_20_s0/Q</td>
</tr>
<tr>
<td>1.183</td>
<td>0.388</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[4]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.843</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.388, 65.865%; tC2Q: 0.201, 34.135%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.340</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.183</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_17_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C23[0][A]</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_17_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R25C23[0][A]</td>
<td style=" font-weight:bold;">eth_udp_mii_inst/ip_receive_inst/rec_data_17_s0/Q</td>
</tr>
<tr>
<td>1.183</td>
<td>0.388</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/DI[1]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.843</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.388, 65.865%; tC2Q: 0.201, 34.135%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.349</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.192</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_30_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C28[2][B]</td>
<td>eth_udp_mii_inst/ip_receive_inst/rec_data_30_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R24C28[2][B]</td>
<td style=" font-weight:bold;">eth_udp_mii_inst/ip_receive_inst/rec_data_30_s0/Q</td>
</tr>
<tr>
<td>1.192</td>
<td>0.396</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[8]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s/DI[6]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[8]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKA</td>
</tr>
<tr>
<td>0.843</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[8]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.396, 66.204%; tC2Q: 0.202, 33.796%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.350</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_2_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R29C25[2][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_2_s0/Q</td>
</tr>
<tr>
<td>1.062</td>
<td>0.266</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADA[5]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.266, 56.879%; tC2Q: 0.202, 43.121%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.351</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_8_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>R29C22[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_8_s0/Q</td>
</tr>
<tr>
<td>1.062</td>
<td>0.266</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADB[11]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKB</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.266, 56.884%; tC2Q: 0.202, 43.116%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.351</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C24[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_5_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>8</td>
<td>R29C24[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_5_s0/Q</td>
</tr>
<tr>
<td>1.062</td>
<td>0.266</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADA[8]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.266, 56.884%; tC2Q: 0.202, 43.116%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.351</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_8_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>R29C22[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_8_s0/Q</td>
</tr>
<tr>
<td>1.062</td>
<td>0.266</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/ADB[11]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKB</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.266, 56.884%; tC2Q: 0.202, 43.116%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.352</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.063</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_3_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>12</td>
<td>R29C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_3_s0/Q</td>
</tr>
<tr>
<td>1.063</td>
<td>0.268</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADA[6]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.268, 56.986%; tC2Q: 0.202, 43.014%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.352</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.064</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_10_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>8</td>
<td>R29C26[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_10_s0/Q</td>
</tr>
<tr>
<td>1.064</td>
<td>0.268</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADA[13]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.268, 56.991%; tC2Q: 0.202, 43.009%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.352</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.064</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C17[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_10_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>8</td>
<td>R29C17[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_10_s0/Q</td>
</tr>
<tr>
<td>1.064</td>
<td>0.268</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/ADB[13]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.268, 56.991%; tC2Q: 0.202, 43.009%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.352</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.064</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C17[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_9_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>8</td>
<td>R29C17[2][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_9_s0/Q</td>
</tr>
<tr>
<td>1.064</td>
<td>0.268</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/ADB[12]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.268, 56.991%; tC2Q: 0.202, 43.009%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.352</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.064</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C23[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_0_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>8</td>
<td>R27C23[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_0_s0/Q</td>
</tr>
<tr>
<td>1.064</td>
<td>0.268</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADB[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKB</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.268, 56.996%; tC2Q: 0.202, 43.004%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.352</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.064</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C25[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.wbin_0_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R27C25[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.wbin_0_s0/Q</td>
</tr>
<tr>
<td>1.064</td>
<td>0.268</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/ADA[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.268, 56.996%; tC2Q: 0.202, 43.004%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.352</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.064</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C23[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_0_s0/CLK</td>
</tr>
<tr>
<td>0.796</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>8</td>
<td>R27C23[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_0_s0/Q</td>
</tr>
<tr>
<td>1.064</td>
<td>0.268</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/ADB[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKB</td>
</tr>
<tr>
<td>0.712</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.268, 56.996%; tC2Q: 0.202, 43.004%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.691</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.839</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>26.529</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_w_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>20.943</td>
<td>0.943</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C23[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_w_1_s0/CLK</td>
</tr>
<tr>
<td>21.175</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>28</td>
<td>R29C23[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_w_1_s0/Q</td>
</tr>
<tr>
<td>21.839</td>
<td>0.663</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s4/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>25.000</td>
<td>25.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>25.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val</td>
</tr>
<tr>
<td>25.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>3</td>
<td>R27C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>26.599</td>
<td>1.599</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4/G</td>
</tr>
<tr>
<td>26.564</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
<tr>
<td>26.529</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.656</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.943, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.663, 74.087%; tC2Q: 0.232, 25.913%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.599, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.678</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>34.067</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Empty_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.358</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C27[3][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n491_s0/I1</td>
</tr>
<tr>
<td>33.913</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R27C27[3][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n491_s0/F</td>
</tr>
<tr>
<td>34.067</td>
<td>0.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C27[2][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Empty_s0/PRESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Empty_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Empty_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C27[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/Empty_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.555, 22.099%; route: 1.724, 68.663%; tC2Q: 0.232, 9.238%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.678</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>34.067</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rempty_val1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.358</td>
<td>1.570</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C27[3][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n491_s0/I1</td>
</tr>
<tr>
<td>33.913</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R27C27[3][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n491_s0/F</td>
</tr>
<tr>
<td>34.067</td>
<td>0.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C27[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rempty_val1_s0/PRESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rempty_val1_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rempty_val1_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C27[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rempty_val1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.555, 22.099%; route: 1.724, 68.663%; tC2Q: 0.232, 9.238%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.227</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.342</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>8</td>
<td>BSRAM_R28[8]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s/RESETB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[8]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKB</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s</td>
</tr>
<tr>
<td>40.342</td>
<td>-0.438</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[8]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.227</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.342</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>8</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/RESETB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKB</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td>40.342</td>
<td>-0.438</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.227</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.342</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>8</td>
<td>BSRAM_R28[6]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/RESETB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKB</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
<tr>
<td>40.342</td>
<td>-0.438</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.227</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.342</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>8</td>
<td>BSRAM_R28[5]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/RESETB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
<tr>
<td>40.342</td>
<td>-0.438</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C27[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_0_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_0_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C27[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C27[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_1_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_1_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C27[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C22[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_2_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_2_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C22[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C22[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C18[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C18[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_4_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_4_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C18[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C19[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C19[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_5_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_5_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C19[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C18[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C18[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_6_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_6_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C18[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C22[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_7_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_7_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C22[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C19[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_8_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C19[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_8_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_8_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C19[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C18[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_9_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C18[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_9_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_9_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C18[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C19[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_10_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C19[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_10_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_10_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C19[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C23[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C23[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_0_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_0_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C23[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C27[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_1_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_1_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C27[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C23[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_2_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_2_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C23[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C20[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C20[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_3_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_3_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C20[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C23[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_4_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_4_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C23[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C20[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C20[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_5_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_5_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C20[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.630</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>33.115</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.745</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>30.000</td>
<td>30.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>30.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>31.556</td>
<td>1.556</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>31.788</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>33.115</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C17[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rbin_num_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.815</td>
<td>0.815</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C17[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_6_s0/CLK</td>
</tr>
<tr>
<td>40.780</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_6_s0</td>
</tr>
<tr>
<td>40.745</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C17[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rbin_num_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.741</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.556, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.815, 100.000%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.450</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.645</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.195</td>
</tr>
<tr>
<td class="label">From</td>
<td>rtl8201_initialize_inst0/rphyrst_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk1m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk1m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[2][A]</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/CLK</td>
</tr>
<tr>
<td>0.386</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R17C22[2][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/rphyrst_s0/Q</td>
</tr>
<tr>
<td>0.645</td>
<td>0.259</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C23[0][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/mdio_inst0/ct_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C23[0][A]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_4_s0/CLK</td>
</tr>
<tr>
<td>0.195</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C23[0][A]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.259, 56.179%; tC2Q: 0.202, 43.821%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.450</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.645</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.195</td>
</tr>
<tr>
<td class="label">From</td>
<td>rtl8201_initialize_inst0/rphyrst_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk1m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk1m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[2][A]</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/CLK</td>
</tr>
<tr>
<td>0.386</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R17C22[2][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/rphyrst_s0/Q</td>
</tr>
<tr>
<td>0.645</td>
<td>0.259</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C23[0][B]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/mdio_inst0/ct_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C23[0][B]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_6_s0/CLK</td>
</tr>
<tr>
<td>0.195</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C23[0][B]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.259, 56.179%; tC2Q: 0.202, 43.821%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.467</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.662</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.195</td>
</tr>
<tr>
<td class="label">From</td>
<td>rtl8201_initialize_inst0/rphyrst_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk1m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk1m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[2][A]</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/CLK</td>
</tr>
<tr>
<td>0.386</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R17C22[2][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/rphyrst_s0/Q</td>
</tr>
<tr>
<td>0.662</td>
<td>0.276</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[1][B]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/mdio_inst0/ct_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[1][B]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_7_s0/CLK</td>
</tr>
<tr>
<td>0.195</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C22[1][B]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.276, 57.755%; tC2Q: 0.202, 42.245%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.467</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.662</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.195</td>
</tr>
<tr>
<td class="label">From</td>
<td>rtl8201_initialize_inst0/rphyrst_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk1m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk1m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[2][A]</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/CLK</td>
</tr>
<tr>
<td>0.386</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R17C22[2][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/rphyrst_s0/Q</td>
</tr>
<tr>
<td>0.662</td>
<td>0.276</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[0][B]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/mdio_inst0/ct_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[0][B]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_0_s0/CLK</td>
</tr>
<tr>
<td>0.195</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C22[0][B]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.276, 57.755%; tC2Q: 0.202, 42.245%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.467</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.662</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.195</td>
</tr>
<tr>
<td class="label">From</td>
<td>rtl8201_initialize_inst0/rphyrst_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk1m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk1m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[2][A]</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/CLK</td>
</tr>
<tr>
<td>0.386</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R17C22[2][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/rphyrst_s0/Q</td>
</tr>
<tr>
<td>0.662</td>
<td>0.276</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[0][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/mdio_inst0/ct_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[0][A]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_3_s0/CLK</td>
</tr>
<tr>
<td>0.195</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C22[0][A]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.276, 57.755%; tC2Q: 0.202, 42.245%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.467</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.662</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.195</td>
</tr>
<tr>
<td class="label">From</td>
<td>rtl8201_initialize_inst0/rphyrst_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk1m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk1m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[2][A]</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/CLK</td>
</tr>
<tr>
<td>0.386</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R17C22[2][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/rphyrst_s0/Q</td>
</tr>
<tr>
<td>0.662</td>
<td>0.276</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[2][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/mdio_inst0/ct_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[2][A]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_5_s0/CLK</td>
</tr>
<tr>
<td>0.195</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C22[2][A]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.276, 57.755%; tC2Q: 0.202, 42.245%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.587</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.782</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.195</td>
</tr>
<tr>
<td class="label">From</td>
<td>rtl8201_initialize_inst0/rphyrst_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ready_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk1m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk1m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[2][A]</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/CLK</td>
</tr>
<tr>
<td>0.386</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R17C22[2][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/rphyrst_s0/Q</td>
</tr>
<tr>
<td>0.782</td>
<td>0.396</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C23[0][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/mdio_inst0/ready_s5/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C23[0][A]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ready_s5/CLK</td>
</tr>
<tr>
<td>0.195</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C23[0][A]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ready_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.396, 66.228%; tC2Q: 0.202, 33.772%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.587</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.782</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.195</td>
</tr>
<tr>
<td class="label">From</td>
<td>rtl8201_initialize_inst0/rphyrst_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk1m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk1m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[2][A]</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/CLK</td>
</tr>
<tr>
<td>0.386</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R17C22[2][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/rphyrst_s0/Q</td>
</tr>
<tr>
<td>0.782</td>
<td>0.396</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[0][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/mdio_inst0/ct_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[0][A]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_1_s0/CLK</td>
</tr>
<tr>
<td>0.195</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C24[0][A]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.396, 66.228%; tC2Q: 0.202, 33.772%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.587</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.782</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.195</td>
</tr>
<tr>
<td class="label">From</td>
<td>rtl8201_initialize_inst0/rphyrst_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk1m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk1m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[2][A]</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/CLK</td>
</tr>
<tr>
<td>0.386</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R17C22[2][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/rphyrst_s0/Q</td>
</tr>
<tr>
<td>0.782</td>
<td>0.396</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/mdio_inst0/ct_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_2_s0/CLK</td>
</tr>
<tr>
<td>0.195</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C24[0][B]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ct_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.396, 66.228%; tC2Q: 0.202, 33.772%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.705</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.900</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.195</td>
</tr>
<tr>
<td class="label">From</td>
<td>rtl8201_initialize_inst0/rphyrst_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ack_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk1m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk1m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[2][A]</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/CLK</td>
</tr>
<tr>
<td>0.386</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R17C22[2][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/rphyrst_s0/Q</td>
</tr>
<tr>
<td>0.900</td>
<td>0.514</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[1][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/mdio_inst0/ack_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[1][A]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ack_s1/CLK</td>
</tr>
<tr>
<td>0.195</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C22[1][A]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/ack_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.514, 71.794%; tC2Q: 0.202, 28.206%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.242</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.195</td>
</tr>
<tr>
<td class="label">From</td>
<td>rtl8201_initialize_inst0/rphyrst_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rtl8201_initialize_inst0/mdio_inst0/rmdio_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk1m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk1m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C22[2][A]</td>
<td>rtl8201_initialize_inst0/rphyrst_s0/CLK</td>
</tr>
<tr>
<td>0.386</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R17C22[2][A]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/rphyrst_s0/Q</td>
</tr>
<tr>
<td>1.242</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT9[B]</td>
<td style=" font-weight:bold;">rtl8201_initialize_inst0/mdio_inst0/rmdio_s0/PRESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk1m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>60</td>
<td>PLL_L[0]</td>
<td>pll_1m_0/rpll_inst/CLKOUTD</td>
</tr>
<tr>
<td>0.184</td>
<td>0.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT9[B]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/rmdio_s0/CLK</td>
</tr>
<tr>
<td>0.195</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT9[B]</td>
<td>rtl8201_initialize_inst0/mdio_inst0/rmdio_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.907%; tC2Q: 0.202, 19.093%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.184, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.440</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.045</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.605</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Full_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R29C22[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_3_s0/Q</td>
</tr>
<tr>
<td>0.915</td>
<td>0.120</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C22[3][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s2/I3</td>
</tr>
<tr>
<td>1.225</td>
<td>0.310</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R29C22[3][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/wfull_val_s2/F</td>
</tr>
<tr>
<td>1.351</td>
<td>0.126</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C22[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n678_s0/I1</td>
</tr>
<tr>
<td>1.661</td>
<td>0.310</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R27C22[0][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n678_s0/F</td>
</tr>
<tr>
<td>2.045</td>
<td>0.384</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C26[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Full_s1/PRESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C26[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_s1/CLK</td>
</tr>
<tr>
<td>0.605</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R27C26[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/Full_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.620, 42.723%; route: 0.630, 43.427%; tC2Q: 0.201, 13.850%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.440</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.045</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.605</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk25m:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R29C22[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_3_s0/Q</td>
</tr>
<tr>
<td>0.915</td>
<td>0.120</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C22[3][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val_s2/I3</td>
</tr>
<tr>
<td>1.225</td>
<td>0.310</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R29C22[3][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/wfull_val_s2/F</td>
</tr>
<tr>
<td>1.351</td>
<td>0.126</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C22[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n678_s0/I1</td>
</tr>
<tr>
<td>1.661</td>
<td>0.310</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R27C22[0][A]</td>
<td style=" background: #97FFFF;">fifo_2048x32_inst/fifo_inst/n678_s0/F</td>
</tr>
<tr>
<td>2.045</td>
<td>0.384</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C26[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/wfull_val1_s1/PRESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>0.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C26[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s1/CLK</td>
</tr>
<tr>
<td>0.605</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R27C26[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/wfull_val1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.620, 42.723%; route: 0.630, 43.427%; tC2Q: 0.201, 13.850%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.548</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.189</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.641</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>41.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>41.333</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>42.189</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>8</td>
<td>BSRAM_R28[8]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s/RESETB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[8]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s/CLKB</td>
</tr>
<tr>
<td>40.629</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s</td>
</tr>
<tr>
<td>40.641</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[8]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_3_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.537</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.548</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.189</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.641</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>41.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>41.333</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>42.189</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>8</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/RESETB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s/CLKB</td>
</tr>
<tr>
<td>40.629</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
<tr>
<td>40.641</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.537</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.548</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.189</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.641</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>41.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>41.333</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>42.189</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>8</td>
<td>BSRAM_R28[6]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/RESETB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s/CLKB</td>
</tr>
<tr>
<td>40.629</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
<tr>
<td>40.641</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[6]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.537</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.548</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.189</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.641</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>41.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>41.333</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>42.189</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>8</td>
<td>BSRAM_R28[5]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/RESETB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s/CLKB</td>
</tr>
<tr>
<td>40.629</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
<tr>
<td>40.641</td>
<td>0.012</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[5]</td>
<td>fifo_2048x32_inst/fifo_inst/Equal.mem_Equal.mem_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.537</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.549</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.189</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.640</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>41.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>41.333</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>42.189</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_0_s0/CLK</td>
</tr>
<tr>
<td>40.629</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_0_s0</td>
</tr>
<tr>
<td>40.640</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R27C27[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.537</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.549</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.189</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.640</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>41.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>41.333</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>42.189</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C27[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_1_s0/CLK</td>
</tr>
<tr>
<td>40.629</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_1_s0</td>
</tr>
<tr>
<td>40.640</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R27C27[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.537</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.549</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.189</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.640</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>41.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>41.333</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>42.189</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_2_s0/CLK</td>
</tr>
<tr>
<td>40.629</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_2_s0</td>
</tr>
<tr>
<td>40.640</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C22[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.537</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.549</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.189</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.640</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>41.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>41.333</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>42.189</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[0][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0/CLK</td>
</tr>
<tr>
<td>40.629</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0</td>
</tr>
<tr>
<td>40.640</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C22[0][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.537</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.549</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.189</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.640</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>41.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>41.333</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>42.189</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C18[1][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C18[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_4_s0/CLK</td>
</tr>
<tr>
<td>40.629</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_4_s0</td>
</tr>
<tr>
<td>40.640</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C18[1][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.537</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.549</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.189</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.640</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>41.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>41.333</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>42.189</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C19[1][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C19[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_5_s0/CLK</td>
</tr>
<tr>
<td>40.629</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_5_s0</td>
</tr>
<tr>
<td>40.640</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C19[1][B]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.537</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.549</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.189</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.640</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>41.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>41.333</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>42.189</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C18[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C18[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_6_s0/CLK</td>
</tr>
<tr>
<td>40.629</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_6_s0</td>
</tr>
<tr>
<td>40.640</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C18[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.537</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.549</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>42.189</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>40.640</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n4_6:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk25m:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>15</td>
<td>R29C24[2][A]</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>41.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C23[2][B]</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
<tr>
<td>41.333</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>28</td>
<td>R29C23[2][B]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/reset_r_1_s0/Q</td>
</tr>
<tr>
<td>42.189</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[0][A]</td>
<td style=" font-weight:bold;">fifo_2048x32_inst/fifo_inst/rptr_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>40.000</td>
<td>40.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk25m</td>
</tr>
<tr>
<td>40.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>448</td>
<td>R29C38[2][A]</td>
<td>clk_25m_s0/Q</td>
</tr>
<tr>
<td>40.594</td>
<td>0.594</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C22[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_7_s0/CLK</td>
</tr>
<tr>
<td>40.629</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>fifo_2048x32_inst/fifo_inst/rptr_7_s0</td>
</tr>
<tr>
<td>40.640</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C22[0][A]</td>
<td>fifo_2048x32_inst/fifo_inst/rptr_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.537</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.131, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.594, 100.000%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.379</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.379</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>n4_6</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>rmii_to_mii_inst/eth_rx_data_3_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>6.757</td>
<td>1.757</td>
<td>tNET</td>
<td>FF</td>
<td>rmii_to_mii_inst/eth_rx_data_3_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>11.136</td>
<td>1.136</td>
<td>tNET</td>
<td>RR</td>
<td>rmii_to_mii_inst/eth_rx_data_3_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.379</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.379</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>n4_6</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>rmii_to_mii_inst/eth_rx_data_2_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>6.757</td>
<td>1.757</td>
<td>tNET</td>
<td>FF</td>
<td>rmii_to_mii_inst/eth_rx_data_2_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>11.136</td>
<td>1.136</td>
<td>tNET</td>
<td>RR</td>
<td>rmii_to_mii_inst/eth_rx_data_2_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.379</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.379</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>n4_6</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>rmii_to_mii_inst/eth_rx_data_0_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>6.757</td>
<td>1.757</td>
<td>tNET</td>
<td>FF</td>
<td>rmii_to_mii_inst/eth_rx_data_0_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>11.136</td>
<td>1.136</td>
<td>tNET</td>
<td>RR</td>
<td>rmii_to_mii_inst/eth_rx_data_0_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.382</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.382</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>n4_6</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>rmii_to_mii_inst/eth_rx_dv_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>6.749</td>
<td>1.749</td>
<td>tNET</td>
<td>FF</td>
<td>rmii_to_mii_inst/eth_rx_dv_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>11.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>rmii_to_mii_inst/eth_rx_dv_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.382</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.382</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>n4_6</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>rmii_to_mii_inst/eth_rx_data_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>6.749</td>
<td>1.749</td>
<td>tNET</td>
<td>FF</td>
<td>rmii_to_mii_inst/eth_rx_data_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>11.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>rmii_to_mii_inst/eth_rx_data_1_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.382</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.382</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>n4_6</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>eth_udp_mii_inst/ip_receive_inst/eth_rxdv_reg_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>6.749</td>
<td>1.749</td>
<td>tNET</td>
<td>FF</td>
<td>eth_udp_mii_inst/ip_receive_inst/eth_rxdv_reg_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>11.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>eth_udp_mii_inst/ip_receive_inst/eth_rxdv_reg_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.382</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.382</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>n4_6</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_0_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>6.749</td>
<td>1.749</td>
<td>tNET</td>
<td>FF</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_0_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>11.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_0_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.382</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.382</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>n4_6</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>6.749</td>
<td>1.749</td>
<td>tNET</td>
<td>FF</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>11.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>fifo_2048x32_inst/fifo_inst/reset_r_1_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.382</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.382</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>n4_6</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>eth_udp_mii_inst/ip_receive_inst/eth_rx_data_reg_3_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>6.749</td>
<td>1.749</td>
<td>tNET</td>
<td>FF</td>
<td>eth_udp_mii_inst/ip_receive_inst/eth_rx_data_reg_3_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>11.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>eth_udp_mii_inst/ip_receive_inst/eth_rx_data_reg_3_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.382</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.382</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>n4_6</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>eth_udp_mii_inst/ip_receive_inst/eth_rx_data_reg_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>6.749</td>
<td>1.749</td>
<td>tNET</td>
<td>FF</td>
<td>eth_udp_mii_inst/ip_receive_inst/eth_rx_data_reg_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>n4_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>fifo_2048x32_inst/fifo_inst/n4_s2/F</td>
</tr>
<tr>
<td>11.131</td>
<td>1.131</td>
<td>tNET</td>
<td>RR</td>
<td>eth_udp_mii_inst/ip_receive_inst/eth_rx_data_reg_1_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>448</td>
<td>clk_25m</td>
<td>1.850</td>
<td>0.943</td>
</tr>
<tr>
<td>60</td>
<td>mdc_d</td>
<td>996.482</td>
<td>0.427</td>
</tr>
<tr>
<td>57</td>
<td>cnt[1]</td>
<td>34.285</td>
<td>1.147</td>
</tr>
<tr>
<td>51</td>
<td>cnt[0]</td>
<td>34.077</td>
<td>1.313</td>
</tr>
<tr>
<td>51</td>
<td>cnt[2]</td>
<td>34.481</td>
<td>0.994</td>
</tr>
<tr>
<td>48</td>
<td>n447_8</td>
<td>7.453</td>
<td>0.932</td>
</tr>
<tr>
<td>46</td>
<td>n3147_5</td>
<td>36.917</td>
<td>1.975</td>
</tr>
<tr>
<td>44</td>
<td>sw_en</td>
<td>37.020</td>
<td>0.977</td>
</tr>
<tr>
<td>44</td>
<td>n1099_3</td>
<td>35.163</td>
<td>1.942</td>
</tr>
<tr>
<td>33</td>
<td>crc_clr_Z</td>
<td>37.546</td>
<td>0.965</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R22C29</td>
<td>93.06%</td>
</tr>
<tr>
<td>R29C23</td>
<td>88.89%</td>
</tr>
<tr>
<td>R24C21</td>
<td>83.33%</td>
</tr>
<tr>
<td>R21C35</td>
<td>83.33%</td>
</tr>
<tr>
<td>R21C40</td>
<td>83.33%</td>
</tr>
<tr>
<td>R18C39</td>
<td>81.94%</td>
</tr>
<tr>
<td>R24C37</td>
<td>81.94%</td>
</tr>
<tr>
<td>R18C38</td>
<td>81.94%</td>
</tr>
<tr>
<td>R21C34</td>
<td>81.94%</td>
</tr>
<tr>
<td>R22C18</td>
<td>80.56%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name sys_clk -period 37.037 -waveform {0 18.518} [get_ports {sys_clk}]</td>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name clk1m -period 1000 -waveform {0 500} [get_nets {mdc_d}]</td>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name clk25m -period 40 -waveform {0 20} [get_nets {clk_25m}]</td>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name eth_clk -period 20 -waveform {0 10} [get_ports {eth_clk}]</td>
</tr>
<tr>
<td>TC_FALSE_PATH</td>
<td>Actived</td>
<td>set_false_path -from [get_clocks {clk25m}] -to [get_clocks {sys_clk}] </td>
</tr>
</table>
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